Fin field effect transistors (finFETs) demonstrate several advantages over planar FETs in terms of, for example, (i) reduced power consumption, (ii) improved threshold voltage control, (iii) channel control, and (iv) leakage current characteristics. However, due to the surface area between the fin and the gate, parasitic capacitances (e.g., between the source/drain (S/D) contacts and the gate structure) may be larger for finFETs as compared to planar FETs. Parasitic capacitances can adversely impact the finFET's cutoff frequency (fT), which sets a boundary for the finFET's frequency response.